Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a clock mixing circuit of a semiconductor device.
A synchronous semiconductor memory device such as a double data rate synchronous dynamic random access memory (DDR SDRAM) is designed to transfer data to external devices by using an internal clock synchronized with an external clock inputted from an external device, such as a memory controller (CTRL).
In order to stably transfer data between a memory device and a memory controller, a temporal synchronization between an external clock applied from the memory controller and data outputted from the memory device is very important.
The memory device outputs data in synchronization with an internal clock. The internal clock is synchronized with the external clock when it is initially applied to the memory device, but the internal clock is delayed while passing through elements within the memory device. Thus, the data is outputted to the outside of the memory device in such a state that it may not be synchronized with the external clock.
In order to stably transfer data outputted from the memory device, the internal clock, delayed while passing through the elements within the memory device, must exactly match the edge or center of the external clock applied from the memory controller. To this end, the internal clock may be synchronized with the external clock by reversely compensating time for loading the data on a bus.
Examples of a clock synchronization circuit for playing such a role include a phase locked loop (PLL) circuit and a delay locked loop (DLL) circuit.
When frequencies of the external clock and the internal clock are different from each other, a PLL circuit is used because a frequency multiplication function is needed. On the other hand, when frequencies of the external clock and the internal clock are equal to each other, a DLL circuit is used because it is not greatly influenced by noise and can be implemented in a relatively small area, as compared to the PLL circuit.
Accordingly, since semiconductor memory devices commonly use the same frequency for both the external clock and the internal clock, the DLL circuit is widely used as the clock synchronization circuit.
In particular, a register controlled DLL circuit is widely used in semiconductor memory devices. The register controlled DLL circuit includes a register which may store a locking delay value. When the power is interrupted, the locking delay value is stored in the register. Then, when the power is again supplied, the locking delay value stored in the register is loaded and used to lock the internal clock. Thus, in the initial operation of the semiconductor memory device, a clock synchronization operation may be performed at a timing at which a phase difference between the internal clock and the external clock is relatively small. After the initial operation of the semiconductor memory device, time taken to synchronize the internal clock with the external clock may be reduced by adjusting the variation range of the delay value of the register according to the phase difference between the internal clock and the external clock.
FIG. 1 is a block diagram illustrating the configuration of a known register controlled DLL circuit.
Referring to FIG. 1, the known register controlled DLL circuit includes a clock buffering unit 100, a divider 180, a phase comparison unit 120, a clock delay unit 140, and a delay replica model unit 160. The clock buffering unit 100 is configured to buffer a positive source clock CLK and a negative source clock CLKB inputted from the outside. The divider 180 is configured to divide a frequency of a reference clock REFCLK corresponding to a clock edge of the positive source clock CLK according to a preset ratio, and output a division reference clock REFCLK_DIV. The phase comparison unit 120 is configured to compare a phase of the division reference clock REFCLK_DIV with a phase of a feedback clock FEEDBACK_CLK. The clock delay unit 140 is configured to delay a phase of a first internal clock RCLK corresponding to a clock edge of the positive source clock CLK, a phase of a second internal clock signal FCLK corresponding to a clock edge of the negative source clock CLKB, and a phase of the division reference clock REFCLK_DIV by a delay amount corresponding to an output signal PHASE_COMP of the phase comparison unit 120. The delay replica model unit 160 is configured to output the feedback clock FEEDBACK_CLK by reflecting an actual delay condition of the source clocks CLK and CLKB into an output clock REFCLK_DIV_DELAY of the clock delay unit 140 corresponding to the inputted division reference clock REFCLK_DIV.
The clock buffering unit 100 includes a positive clock buffer 102, a negative clock buffer 104, and a dummy clock buffer 106. The positive clock buffer 102 is configured to buffer the positive source clock CLK and output the first internal clock RCLK. The negative clock buffer 104 is configured to buffer the negative source clock CLKB and output the second internal clock FCLK. The dummy clock buffer 106 is configured to buffer the positive source clock CLK and output the reference clock REFCLK.
Also, the clock delay unit 140 includes a first delay section 142, a second delay section 144, a dummy delay section 146, and a delay control section 148. The first delay section 142 is configured to delay a phase of the first internal clock RCLK in response to a delay control signal DELAY_CON. The second delay section 144 is configured to delay a phase of the second internal clock FCLK in response to the delay control signal DELAY_CON. The dummy delay section 146 is configured to delay a phase of the division reference clock REFCLK_DIV_DELAY in response to the delay control signal DELAY_CON. The delay control section 148 is configured to change a logic level of the delay control signal DELAY_CON in response to the output signal PHASE_COMP of the phase comparison unit 120.
FIG. 2 is a block diagram illustrating a delay section of the clock delay unit in the known register controlled DLL circuit of FIG. 1.
Referring to FIG. 2, the delay sections 142, 144, and 146 of the clock delay unit 140 in the known register controlled DLL circuit each include a first delay line 200, a second delay line 220, and a is phase mixer 240. The first delay line 200 includes a plurality of delay units DU1, DU2, DU3, DU4, DU5, DU6, DU7 and DU8 coupled in series, and delays the first internal clock RCLK, the second internal clock FCLK, or the division reference clock REFCLK_DIV through an odd number of the delay units, which are in a preset order, in response to the delay control signal DELAY_CON. The second delay line 220 includes a plurality of delay units DU1, DU2, DU3, DU4, DU5, DU6, DU7 and DU8 coupled in series, and delays the first internal clock RCLK, the second internal clock FCLK, or the division reference clock REFCLK_DIV through an even number of the delay units, which are in a preset order, in response to the delay control signal DELAY_CON. The phase mixer 240 is configured to mix a phase of a clock DU_CLK_1 outputted from the first delay line 200 and a phase of a clock DU_CLK_2 outputted from the second delay line 220 at a ratio corresponding to the delay control signal DELAY_CON.
FIG. 3 is a block diagram illustrating a known phase mixer among the elements of the delay section of FIG. 2.
Referring to FIG. 3, the known phase mixer 240 of the delay sections 142, 144, and 146 of the clock delay unit 140 includes a plurality of mixing control signal generators 242<1>, 242<2>, 242<3>, . . . , 242<N>, and a clock mixer 244. The plurality of mixing control signal generators 242<1>, 242<2>, 242<3>, . . . , 242<N> are configured to generate a plurality of mixing control signals MIX_CON<1>, . . . , MIX_CON<2>, MIX_CON<3>, . . . , MIX_CON<N>, MIX_CONB<1>, MIX_CONB<2>, MIX_CONB<3>, . . . , MIX_CONB<N> in response to mixing ratio control signals SHIFT_LEFT and SHIFT_RIGHT corresponding to the delay control signal DELAY_CON. The clock mixer 244 is configured to generate a mixing clock MIX_CLK by mixing a first driving clock DRV_DU_CLK_1 and a second driving clock DRV_DU_CLK_2. The first driving clock DRV_DU_CLK_1 is generated by driving the clock DU_CLK_1 outputted from the first delay line 200 according to the plurality of positive mixing control signals MIX_CON<1>, MIX_CON<2>, MIX_CON<3>, . . . , MIX_CON<N>. The second driving clock DRV_DU_CLK_2 is generated by driving the clock DU_CLK_2 outputted from the second delay line 220 according to the plurality of negative mixing control signals MIX_CONB<1>, MIX_CONB<2>, MIX_CONB<3>, . . . , MIX_CONB<N>.
The clock mixer 244 includes a plurality of first drivers 2442<1>, 2442<2>, 2442<3>, . . . , 2442<N>, a plurality of second drivers 2444<1>, 2444<2>, 2444<3>, . . . , 2444<N>, and a clock combiner 2446. The plurality of first drivers 2442<1>, 2442<2>, 2442<3>, . . . , 2442<N> are configured to output the first driving clock DRV_DU_CLK_1 by driving and combining the clock DU_CLK_1 outputted from the first delay line 200 in response to the plurality of positive mixing control signals MIX_CON<1>, MIX_CON<2>, MIX_CON<3>, . . . , MIX_CON<N>. The plurality of second drivers 2444<1>, 2444<2>, 2444<3>, . . . , 2444<N> are configured to output the second driving clock DRV_DU_CLK_2 by driving and combining the clock DU_CLK_2 outputted from the second delay line 220 in response to the plurality of negative mixing control signals MIX_CONB<1>, MIX_CONB<2>, MIX_CONB<3>, . . . , MIX_CONB<N>. The clock combiner 2446 is configured to output the mixing clock MIX_CLK by combining the first driving clock DRV_DU_CLK_1 and the second driving clock DRV_DU_CLK_2.
The operation of the known phase mixer 240 will be described by example below.
Here, it is assumed that each of the delay units DU1 to DU8 delay their respective inputs by a same delay unit amount. Referring to FIGS. 2 and 3, the phase of the clock DU_CLK_1 outputted from the first delay line 200 is in a state such that it is delayed by a delay amount of ½×delay unit amount corresponding to the position “1”, and the phase of the clock DU_CLK_2 outputted from the second delay line 220 is in a state such that it is delayed by a delay amount of (1+½)×delay unit amount corresponding to the position “2”. If the ratio corresponding to the delay control signal DELAY_CON drives the clock DU_CLK_1 outputted from the first delay line 200 at 75% to generate the first driving clock DRV_DU_CLK_1, and drives the clock DU_CLK_2 outputted from the second delay line 220 at 25% to generate the second driving clock DRV_DU_CLK_2, the mixing clock MIX_CLK outputted from the clock combiner 2446 included in the phase mixer 240 is delayed by a delay amount of ¾×delay unit amount corresponding to a ¼×delay unit amount shift from position “1” in the direction of position “2” (see position “3” in FIG. 2).
On the other hand, if the ratio corresponding to the delay control signal DELAY_CON drives the clock DU_CLK_1 outputted from the first delay line 200 at 25% to generate the first driving clock DRV_DU_CLK_1, and drives the clock DU_CLK_2 outputted from the second delay line 220 at 75% to generate the second driving clock DRV_DU_CLK_2, the mixing clock MIX_CLK outputted from the clock combiner 2446 included in the phase mixer 240 is delayed by a delay amount of (1+¼)×delay unit amount corresponding to a ¾×delay unit amount shift from position “1” in the direction of position “2” (see position “4” in FIG. 2).
As described above, the phase mixer 240 may select a delay amount smaller than that of the delay unit and delay the clock. At this time, the phase mixer 240 can select the value of the delay amount and delay the clock by the selected delay amount according to the number of the first drivers 2442<1>, 2442<2>, 2442<3>, . . . , 2442<N> and the number of the second drivers 2444<1>, 2444<2>, 2444<3>, . . . , 2444<N>.
Meanwhile, when the frequencies of the positive source clock CLK and the negative source clock CLKB inputted from the outside are relatively high, it is advantageous when the delay amount selectable by the phase mixer 240 is relatively small.
On the other hand, when the frequencies of the positive source clock CLK and the negative source clock CLKB inputted from the outside are relatively low, it is advantageous when the delay amount selectable by the phase mixer 240 is relatively large.
However, in the known phase mixer 240, once the number of the first drivers 2442<1>, 2442<2>, 2442<3>, . . . , 2442<N> and the number of the second drivers 2444<1>, 2444<2>, 2444<3>, . . . , 2444<N> are determined, they cannot be changed.
Therefore, in case where the positive source clock CLK and the negative source clock CLKB having frequencies higher or lower than the frequencies determined when designed are applied to the semiconductor device, the performance of the DLL circuit may not be fully exhibited as expected at the time when it is designed.
For example, when the positive source clock CLK and the negative source clock CLKB having frequencies higher than the frequencies determined when designed are applied to the DLL circuit of the semiconductor device, considerable jitters may occur between the positive and negative source clocks CLK and CLKB applied from the outside and the positive and negative output clocks RCLK_DELAY and FCLK_DELAY of the clock delay unit 140, even though the operation of the DLL circuit is completed.
On the other hand, when the positive source clock CLK and the negative source clock CLKB having frequencies lower than the frequencies determined when designed are applied to the DLL circuit of the semiconductor device, much more time is taken to complete the operation of the DLL circuit than expected. Consequently, the operation of the DLL circuit may not be completed.